Counter and shift-register



March 19, 1968 JAMES El WEBB 3,374,339

ADMINISTRATOR OF THE NATIONAL AERONAUTICS AND SPACE ADMINISTRATIONCOUNTER AND SHIFT-REGISTER Filed Dec. 17, 1964 4 Sheets-Sheet 1 3 n nSOURCE OF COUNT SOURCE OF INHIBIT PULSES I I SET PULSES I I j I2 I5 T-SOURCE OF 20 (4 COUNTPULSES g g Ig\ I 4 SOURCE OF RESET PULSES FIG. I

250 SOURCE OF SHIFT T0 INHIBIT PULSES l9 L. l5 T0 GATE l5 or 250PRECEDING STAGE SOURCE OF SHIFT PULSES To GATE 16 0F PRECEDING STAGE IINVENTOR To CHRISTIAN SMITH BY A FIG. 4

ATTORNEYS March 19, 1968 Filed Dec. 17, 1964 JAMES E. WEBB ADMINISTRATOROF' THE NATIONAL AERO-NAUTICS AND SPACE ADMINISTRATION COUNTER ANDSHIFT-REGISTER IhIBIs 3 (k) Dl6 4 Sheets-Sheet 3 I la IIIIZIIIIII Oji-In co :0 IO m cu II A A A E c v v INVENTOIT CHRISTIAN SMITH CNWEQMIATTORNEYS March 19, 1968 JAMES E. WEBB 3, ADMINISTRATOR OF THE NATIONALAERONA'UTICS AND SPACE ADMINISTRATION COUNTER AND SHIFT-REGISTER 4SheetsSheet 4 Filed Dec. 17, 1964 INVENTOR CHRRSTIAN SMITH ATTORNEYS m wE United States Patent Ofifice 3,374,339 Patented Mar. 19, 19683,374,339 COUNTER AND SHIFT-REGISTER James E. Webb, Administrator of theNational Aeronautics and Space Administration, with respect to aninvention of Christian Smith, Salisbury, Southern Rhodesia Filed Dec.17, 1964, Ser. No. 423,412 11 Claims. (Cl. 235-92) The inventiondescribed herein was made in the per formance of work under a NASAcontract and is subject to the provisions of Section 305 of the NationalAeronautics and Space Act of 1958, Public Law 85568 (72 Stat. 435; 42USC 2457).

This invention relates to computer logic circuitry and more particularlyto an improved circuit for performing both counting and shifting logicoperations.

In designing circuits for modern computers, a premium is placed on thereduction of the number of components which are necessary to perform thevarious computers logic operation. Therefore, the trend has been to use,Wherever possible, the same components and circuits to perform more thanone basic operation. Also, with the development of integrated circuitryand the desire to miniaturize circuits and components as much aspossible, a need exists for circuits which, besides being operable toperform more than one logic function, lend themselves tomicrominiaturization construction techniques.

At present, circuits which perform the logic functions both of countingand information shifting are well known in the art. These circuitsgenerally include a plurality of elements including capacitors which areused in the performance of the counting operation, and in particular inshifting the information. The inherent rise-time of capacitors limitsthe response characteristics of such circuits to triggering signals, aswell as increases the sensitivity of the circuits to extraneous noiseand undesired signal pickup. However, the basic disadvantage of usingcapacitors in such counter/shifting circuits is that the circuits cannotbe easily miniaturized since the capacitors generally occupy asignificant amount of space.

In the present state-of-the-art, it is difiicult to fabricatesolid-state miniature capacitors with close tolerances which can beeasily incorporated in microminiaturized circuitry. Also, solid-statecapacitors are generally temperature-sensitive as well as subject todegradation due to aging effects. Therefore, the need exists for acounter/ shifting circuit which includes only non-capacitive elementsadaptable to miniaturization construction techniques.

Accordingly, it is an object of the present invention to provide a novelcounter/ shifting circuit which is adaptable to microminiaturization.

Another object of the invention is to provide a counter/ shiftingcircuit in which a simple logic gating circuit is used as the basiccircuit element.

Yet another object of the invention is the provision of a circuit inwhich only solid-state noncapacitive components are incorporated in aplurality of Nand gates to perform the necessary counting and shiftingoperations.

A further object of the invention is the provision of a counter/shiftingcircuit in which only noncapaci-tive solidstate components are arrangedin a plurality of Nand gates, the entire circuit being adaptable to beminiaturized or integrated in a basic integrated circuit.

These and other objects are achieved by providing a circuit in whichonly noncapacitive solid-state elements are used in a simple matrixlayout of Nand gates. All the elements used are of the type which are atpresent available in miniature sizes. The elements are directlyintercoupled so that capacitors are not needed to perform either of thetwo desired operations. The simplicity of the matrix layout adapts thecircuit to micromodular integrated circuitry construction techniques.Thus, the size of the circuit may be greatly reduced. Since all basiccomponents are noncapacitive solid-state elements, they can all beintegrated in a simple semiconductive chip or element, further reducingthe size of the circuit as well as the cost of manufacturing.

The novel features that are considered characteristic of this inventionare set forth with particularity in the appended claims. The inventionitself both as to its organization and method of operation, as well asadditional objects and advantages thereof, will best be understood fromthe following description when read in connection with the accompanyingdrawings, in which:

FIGURE 1 is a circuit diagram of a portion of the invention used in acounting mode;

FIGURES 2(a) and 2(b) are schematic diagrams of non-capacitivesolid-state Nand gates;

FIGURE 3 is a diagram of waveforms useful in explaining the operation ofthe novel circuit of the invention;

FIGURE 4 is a circuit diagram of a portion of the invention used in aninformation shifting mode;

FIGURE 5 is a circuit diagram of an arrangement incorporating fourstages of the present invention; and

FIGURE 6 is a chart useful in explaining the operation of thearrangement shown in FIGURE 5.

Reference is now made to FIGURE 1 which is a circuit diagram useful inexplaining the part of the novel circuit of the invention which is usedin the counting operation. As seen therefrom, the circuit comprisesgates 11-16, each having an output terminal or line and two or moreinput terminals or lines. Three input lines of gate 11 are connected tooutput lines of gates 12'and 15 and to a source of set pulses 17athrough a set line 17, respectively. Similarly, the three input lines ofgate 14 are connected to output lines of gates 13 and 16 and to a sourceof reset pulses 18a through a reset line 18. Each of gates 12 and 13have four input lines. Those of gate 12 are connected to the outputlines of gates 11 and 13, and to the line 17 as well as a shift inputline 19. One input line of gate 13- is also connected to line 19 whilethe other three lines are connected to reset line 18 and to output linesof gates 12 and 14 respectively. Single input lines'of gates 15 and 16are connected to output lines of gates 12 and 13 respectively, while theother input of each gate (15 and 16) is connected to the output line ofthe opposite gate.

Each of the gates shown in FIGURE 1 is a solid-state non-capacitive Nandgate which may be thought of as a circuit in which a signal of a givenpolarity on any one of the input lines will cause the gate to produce anoutput signal of an opposite polarity. Two examples of solidstatenon-capacitive gates which produce such signals are shown in FIGURES2(a) and 2( b) to which reference is made herein. As seen in FIGURE2(a), a gate such as gate 11 having three input lines may comprise ofthree transistors 22, 24 and 26, the collectors of the transistors beingconnected together at a junction point 28 which serves as the outputterminal of the gate 11. Point 28 is also used to connect the threecollectors to a source of positive potential B+ (not shown) through aresistor 29. The base of each of the transistors serves as an inputterminal, connecting the gate to one of its input lines.- Each of thetransistors is also connected to ground potential through its respectiveemitter.

From FIGURE 2(a), it is clear to one familiar with the art that thepotential level at the output terminal 28 is high, namely close to B+ aslong as all the transistors 22, 24 and 26 are in their nonconductingstates, which is the case so long as their respective bases are at a lowpotential level, such as ground. However, as soon as an input signalhaving a potential level close to B+ is 3 supplied to any of the bases,the respective transistor is switched to a conducting state, therebylowering the potential level at point 28 from B+ to substantially groundpotential.

It is thus seen that the gate shown in FIGURE 2(a) produces an outputsignal which is represented by a drop in the potential at point 28 inresponse to any input signal which is represented by an increase inpotential level. The basic gate of the present invention may beconstructed to include a single transistor with a plurality of diodessuch as shown in FIGURE 2(1)).

As seen therefrom, the gate 11 comprises a transistor 32 having itscollector serve as the output terminal and its emitter connected toground potential. A resistor 34 interconnects the emitter to the basewhich is connected to the cathode of a diode 36. The anode of diode 36as well as anodes of diodes 37, 38 and 39 are all joined together at apoint 42 which is connected to B+ through a resistor 43. The cathodes ofdiodes 37, 38 and 39 serve as the input terminals of the gate 11. Aslong as the cathodes of diodes 3-7, 38 and 39 are maintained at apotential substantially equal to 13+, current will not flowtherethrough. Consequently, point 42 will be at about B+ potentialthereby maintaining transistor 32 in a conducting state or a lowpotential level at the collector. However, as soon as any one of thecathodes of diodes 37, 38 and 39 is at a low potential level, the levelat point 42 will he reduced to cut-off the transistor 39 and therebyraise the potential of its collector which serves as the outputterminal.

From the foregoing, it is thus seen that either of the gates shown inFIGURES 2(a) and 2(1)) provides an output signal of a known polarity inresponse to an input signal of an opposite polarity which is applied toany of the gates input lines. For explanatory purposes, hereinafter itwill be assumed that as long as all of the input lines are supplied withnegative signals, namely, the inputs are false, the gate will provide apositive signal, or a true output. However, any true input will causethe gate to produce a false output.

Reference is now made to FIGURE 3 which is a diagram of waveforms usefulin explaining the operation of the present invention. Line a representsthe waveform of a plurality of input count pulses 45 supplied to gates12 and 13 (FIGURE 1) through input line 20. The count pulses may besupplied to gates 12 and 13 from a gate similar to gate 14 or 11 of aprevious circuit as shown in FIGURE 1. Similarly, the count pulses maybe supplied from a source of count pulses a. Lines b through g (FIGURE3) represent the waveforms of the outputs of gates 13, 12, 11, 14, 15and 16 respectively. As shown in FIGURE 3, let us assume that at a timet the circuit of FIGURE 1 is set by means of a pulse supplied via line17 to gates 11 and 12 so that thereafter, the output levels of gates1116 are as shown. Namely, gates 12 and 16 are true and all the othersare false.

The first of count pulses is supplied at time t As a result, both gates12 and 13 are supplied with a true input. Gate 13 is unaffected since itis already false. But gate 12, which is true prior to Z is switched to afalse state by the true input pulse. The false output from gate 12 issupplied to gate 11 which now has all its inputs false so that itswitches to a true state. At time b the count pulse 45 terminates sothat gate 13 is no longer supplied with a true input. Consequently, gate13 becomes true which in turn causes gates 12, 14 and 16 to eitherremain or be switched to the false state. With both gates 12 and 16being false, gate 15 is switched to true which in turn switches gate 11to false.

These states will continue until time t;, when the second count pulsestarts. As a result, gate 13 will be switched to false. With gates 13and 16 being false, gate 14 is switched to a true state. At time t.,,the second count pulse 45 terminates, thus there are no longer any trueinputs to gate 12 to maintain it in a false state. Conse- 4 quently,gate 12 switches to true which in turn causes gate 15 to switch tofalse. With both gates 15 and 13 being false, gate 16 becomes true whichin turn causes gate 14 to be switched to the false state.

After t and before t when the next count pulse is initiated, the levelsof the gates 1116 are the same as at time t so that additional pulseswill cause the circuit to merely repeat the sequence of operationhereinbefore described. It is thus seen that for every two input counterpulses, gates 11 and 14 produce single pulses designated in FIGURE 3 bynumerals 46 and 48 respectively. Thus, the circuit of FIGURE 1 may bethought of as a binary divider or counter producing a single pulse forevery two pulses. By connecting the output of gate 14 to the inputs ofgates of a succeeding stage, similar to gates 12 and 13 of the circuitshown in FIGURE 1, an arrangement comprising a plurality of stages iscreated. Each stage in a sense divides by two the number of pulsessupplied from the previous stage, thus the entire arrangement performsas a binary counter.

As previously stated, the novel circuit of the invention, in addition toperforming a counting operation, also operates in an informationshifting mode. In such a mode, gates 11 and 14 (FIGURE 1) of each stageare inhibited, and only gates 12, 13, 15 and 16, together with twoadditional Nand gates are used. Reference is now made to FIGURE 4 whichis a simplified circuit diagram useful in explaining the shiftingoperation of the novel circuit of the present invention. As seentherein, gates 15 and 16 are interconnected in a manner similar to thatshown in FIG- URE 1. Similarly, gates 12 and 13 are interconnected toone another as well as to gates 15 and 16. However, in addition, theoutput of gate 12 is connected to one of the inputs of a Nand gate 19,another input of Nand gate 19 being connected to a gate similar to gate16 of a preceding stage. The output of gate 19 is connected as one inputof gate 12.

Similarly, the output of gate 13 is connected as one input to a Nandgate 21, having another input connected to a Nand gate, similar to gate15, of a preceding stage. The output of gate 21 is connected as oneinput to gate 13. Also, gates 12 and 13 are connected to a junctionpoint 23 through which shift pulses are supplied to both gates from asource of shift pulses 23a, in a manner similar to the count pulsessupplied to the two gates as hereinbefore described.

When operating in the information shifting mode, one or more true shiftpulses are simultaneously supplied to gates 12 and 13 of each of thestages of the circuitry of the present invention. These true shiftpulses cause gates 12 and 13 to produce false output pulses for theduration of the true shift pulses supplied thereto. Thereafter, namelybetween true shift pulses, the gates 12 and 13 of each stage adapt atrue or a false state, depending on the outputs of the gatesinterconnected with them. For example, gates 12 and 13 shown in FIGURE 4produce false outputs during the duration of a true shift pulse suppliedto both gates via the junction point 23. However, after the true shiftpulse terminates, the gate 12 will provide either a true or a falseoutput, depending on the input supplied thereto from the gate 19, whichis in turn also controlled by the output of a gate similar to gate 16from a previous stage. Similarly, the state of gate 13, after thetermination of the true shift pulse, will depend on the output from gate21 as well as the state of gate 12.

In order to insure the proper operation of the circuit of the presentinvention, gates 11 and 14 are inhibited from counting during the shiftoperation, and gates 19 and 21 are inhibited from shifting informationduring the counting operation. As seen from FIGURE 1, gates 11 and 14are so inhibited by being connected to a source of count inhibit pulses27a through a count inhibit line 27 which provides the two gates with atrue input pulse during the shifting operation, thus setting both gates.11 and 14 to a false state. Similarly, gates 19 and 21 (see FIGURE 4)are connected to a source of shift inhibit pulses 250 through a shiftinhibit line 25 which supplies both gates with true input pulses duringthe counting operation so as to set both gates 19 and 21 to a falsestate during the operation in which gates 19 and 21 do not participate.

For a better understanding of the novel circuit of th present invention,as well as the novel operational characteristics thereof, reference isnow made to FIGURE 5 which is a circuit diagram of an arrangementincluding four stages designated A, B, C, and D. Each stage comprisesthe novel counting and shifting circuit of the present inventionemploying only non-capacitive solid-state Nand gates. As seen fromFIGURE 5, the count inhibit lines 27 and shift inhibit lines 25 of allthe four stages are interconnected, While the set line 17 and reset line18 are not connected together so that each stage may be set or resetindividually. Hereinafter, each gate will be designated by the letterdesignation of the stage of which it is a part, as well as itsparticular numeral. Thus, gate 11 of stage A, hereinafter, will berepresented by All.

Reference is again made to FIGURE 3, wherein lines h, j and k representthe levels of the output of gates B16, C16. and D16 respectively. Linesl, m and n of FIGURE 3 represent the levels of the count inhibit line23, the shift inhibit line 25 and the shift pulse line 55 respectively.

Let us assume that from time i (FIGURE 3) to a time i the arrangement ofFIGURE 5 is operated in the counting mode, with count pulses designatedby numeral 45 being supplied to stage A. The output levels of gates Allthrough A16 are shown on lines b through g of FIG- URE 3, with lines h,j, and k representing the output levels of gates B16, C16 and D16respectively. The output levels of all the gates are indicated by plusor minus signs in achart shown inFIGURE 6 to which reference is madeherein. Each column of the chart represents a different gate and eachrow represents a different time period. The plus sign indicates that aparticular ,gate is true, namely, produces a positive output levelwhereas a negative sign indicates that the gate is false.

"Prior to time t such as at time t the gates of stages A through D haveoutput levels as shown on the first line of FIGURE 6. Thereafter, attime t gates 11 and 14 of each stage are inhibited and gates 19 and 21of eachstage are enabled by the respective positive and negative pulsesor levels on the count inhibit line and shift inhibit line shown onlines l and of FIGURE 3. As a result, gates 11 and 14 .of the stageshave false outputs and gates 19 and 21 adapt output levels, depending onthe le'vels'of the gates associated with them. As seen from the line iof FIGURE 6, onlygate D19 changes from false to true. This becomesapparent since after t the two inputs to D19 from D12 and C16 are bothfalse, thus D19 becomes true. Gates ,11 and 14 of all the stages remaininhibited until. a time t when the arrangement is again switched to acount mode, as will be explained hereinafter. At timerthe'first shiftpulse of a group of shift pulses 65 is supplied from the source of shiftpulses 23a via shift pulse line 55 (see line n of FIGURE 3) to gates 12and 13 of each stage. Thus, gates 12 and 13 proyide false outputs whichin turn cause the rest of the gates to adapt the output levels as shownon the third line of FIGURE 6.

I At time 1 the first pulse 65 terminates, thus no longer supplying trueinputs to gates 12 and 13. Consequently,

gates 12 and 13 are free to be set in either a true or a false state,depending on the states of the gates which pulses, the gates may beeither true or false, depending 6 on the inputs supplied thereto. Asseen from FIGURE 6, lines marked i through t represent the outputs ofthe various stages during the period between t and r Also,

the changes in the output levels of B16, C16 and D16 as well as gatesA13, A12, A15 and A16 are shown in FIGURE 3.

At time 13 the levels on count inhibit line 23 and shift inhibit line 25will be switched, thus, terminating the shifting operation by inhibitinggates 19 and 21 of each stage as indicated by the minus signs on thelast line of FIGURE 6 in the columns of gates 19' and 21 and initiatinga new counting mode. At the same time, gates 11 and 14 will no longer beinhibited so that when a subsequent count pulse such as pulse 69 shownon line a of FIGURE 3 is supplied, the arrangement of FIGURE 6 Willagain operate in the counting mode.

From the foregoing description, it is seen that the present inventionprovides a novel circuit which may be arranged in a plurality of stagesto perform counting as well as information shifting operations. Eachstage comprises eight solid-state non-capacitive Nand gates, four gatesof each stage are used for both counting and shifting purposes, While ofthe other four gates, two are used in the counting operation and theother two are used for the shifting operation.

The circuit is most versatile in that data may be read in and out of thevarious stages in parallel. Also single phase shift pulses supplied inparallel to all the stages may be employed. In the shift mode, eachstage samples the state of the previous stage With the leading edge ofeach shift pulse and reads in such shifted data with the trailing edgeof a shift pulse. For example, B16 of stage B reads in the state ofstage A during the trailing edge of the first shift pulse at time t(FIGURE 3). In addition, each stage may be conveniently set and reset bycausing particular gates to be set to the false or true states.

Each stage is completely symmetrical so that complement input signalsmay be used. The gates are all of the Nand type incorporating onlynon-capacitive solid-state components which are directly coupled to oneanother thus providing great simplicity of layout and interconnection.This characteristic particularly adapts the novel circuit of theinvention to modern mircromodular integrated circuit constructiontechniques.

It is apparent to those familiar with the art that modifications may bemade in the arrangement as shown without departing from the true spiritof the invention. Therefore, all such modifications and equivalents aredeemed to fall within the scope of the invention as claimed in theappended claims.

What is claimed is:

1 A counting and shifting circuit comprising: a plurality of gatingmeans, each gating means having an output terminal a plurality of inputterminals and being characterized by providing an output of a firstpolarity on said output terminal whenever none of said input terminalsis provided with an input signal of said first polarity, each of saidgating means being characterized by providing an output signal of asecond polarity whenever an input signal of said first polarity isprovided to any one of the input terminals thereof; means forinterconnecting said first plurality of gating means; count inhibitingmeans for inhibiting at least some of said gating means whenever saidplurality of gating means is opera- .ble in a shifting mode; means forenergizing some of said gating means with a plurality of shift pulses soas to control the outputs of said plurality of gating means; shiftinhibiting means for inhibiting at least some of said gating meanswhenever said circuit is operable in a counting mode; and means forenergizing some of said gating means with counting pulses to provideoutput pulses as a function of the number of said counting pulsessupplied thereto.

2. A circuit for counting count pulses supplied thereto and for shiftingdata in response to shift pulses comprising: first, second and thirdpluralities of gating means each gating means having an output terminala plurality of input terminals and being characterized by providing anoutput of a first polarity on said output terminal Whenever none of saidinput terminals is provided with an input signal of said first polarity,each of said gating means being characterized by providing an outputsignal of a second polarity whenever an input signal of said firstpolarity is provided to any one of the input terminals thereof; meansfor interconnecting said first, second and third pluralities of gatingmeans; shift inhibiting means for inhibiting the gating means of saidsecond plurality of gating means from providing output signals of saidfirst polarity; means for supplying said count pulses to some of saidfirst plurality of gating means to energize said first and thirdpluralities of gating means to count said count pulses; count inhibitingmeans for inhibiting the gating means of said third plurality of gatingmeans from providing output signals of said first polarity; and meansfor supplying to said shift pulses to said some of said first pluralityof gating means to energize said second means and said first means toshift the output signals thereof as a function of said shift pulsessupplied thereto.

3. A circuit for providing count output signals in response to countpulses and for shifting information represented by the levels therein inresponse to shift signals supplied thereto comprising: first, second,third, fourth, fifth, sixth, seventh and eighth gating means each gatingmeans having an output terminal a plurality of input terminals and beingcharacterized by providing an output of a first polarity on said outputterminal whenever none of said input terminals is provided with an inputsignal of said first polarity, each of said gating means beingcharacterized by providing an output signal of a second polaritywhenever an input signal of said first polarity is provided to any oneof the input terminals thereof; means for interconnecting said gatingmeans; shift inhibiting means for selectively inhibiting said fifth andsixth gating means from providing output signals of said first polarity;means for supplying said count pulses to said first and second gatingmeans to control the polarities of the output signals of saidinterconnected first, second, third, fourth, seventh and eighth gatingmeans to provide count output signals from the output terminal of saideighth means as a function of the number of count pulses supplied tosaid first and second gating means; count inhibiting means forselectively inhibiting said seventh and eighth gating means fromproviding output signal of said first polarity; and means for supplyingsaid shift pulses to said first and second gating means to control theshifting of said information as a function of the output signals of saidthird and fourth interconnected gating means.

4. A circuit as recited in claim 3 wherein the input terminals of saidfirst gating means are connected to at least the output terminals ofsaid second, fifth and seventh gating means and to said means forsupplying said count pulses, wherein the input terminals of said secondgating means are connected to at least the output terminals of saidfirst, sixth and eighth gating means and said means for supplying saidcount pulses, the input terminals of said third gating means beingconnected to the output terminals of said first and fourth gating means,the input terminals of said fourth gating means being connected to theoutput terminals of said second and third gating means, the inputterminals of said fifth means being connected at least the outputterminal ofsaid first gating means and to said shift inhibiting means,one input terminal of said sixth gating means being also connectedtosaid shift inhibiting means at least another terminal of said sixthgating means being connected to the output terminal of said secondmeans, the input terminals of said seventh means being connected to atleast the output terminals of said first and third gating means, theinput terminals of said eighth gating means being connected to at leastthe output terminals of said second and fourth gating means and whereinsaid count inhibiting means is connected to input terminal of saidseventh and eighth gates.

5. A circuit as recited in claim 4 wherein each of said gating meanscomprises non-capacitive solid-state means.

6. A circuit as recited in claim 5 wherein said circuit further includessetting means connected to at least the input terminals of said firstand seventh gating means and resetting means connected to at least theinput terminals of said second and eighth gating means for selectivelysetting and resetting said gating means so as to control the outputsignals thereof.

7. In a counting stage comprising of a plurality of interconnected Nandgates each having a single output and a plurality of inputs wherein theoutput of a first Nand gate is connected to the inputs of second, thirdand fourth Nand gates, the output of said second Nand gate beingconnected to the inputs of said first Nand as well as fifth and sixthNand gates, the output of said third Nand gate being connected to theinputs of said fourth and fifth Nand gates, the outputs of said fourthand sixth Nand gates being respectively connected to the inputs of saidfirst and second Nand gates and the output of said fifth Nand gate beingconnected the inputs of said third and sixth Nand gates so as to providea count output signal fr0m the output of at least said sixth Nand gatein response to count pulses supplied to said first and second Nand gatesthe arrangement for energizing said first, second, third and fourth Nandgates so as to shift data therethrough comprising: seventh and eighthNand gates each having an output and a plurality of inputs; means forconnecting the outputs of said first, second, seventh and eighth Nandgates to inputs of said seventh, eighth, first and second Nand gatesrespectively; shift pulse means for providing shift pulses; means forconnecting said shift pulse means to inputs of said first and secondNand gates so as to provide said shift pulses thereto to shift datatherethrough; count inhibit means for providing count inhibit pulses;means for connecting said count inhibit means to inputs of said fourthand sixth Nand gates so as to selectively inhibit said gates fromproviding an output of a predetermined polarity whenever said first,second, third, fourth, seventh and eighth Nand gates are operable toshift data therethrough; count pulse means for providingcount pulses;means for connecting said first and second Nand gates to provide saidcount pulses thereto to control the outputs of said first, second,third, fourth, fifth and sixth Nand gates so as to provide count outputsignals as a function of the number of count pulses supplied to saidfirst and second Nand gates; shift inhibit means for providing shiftinhibit pulses; and means for connecting said shift inhibit means toinputs of said seventh and eighth Nand gates so as to selectivelyinhibit said gates from providing an output of a predetermined polaritywhenever said seventh and eighth Nand gates are not operable to shiftdata therethrough.

8. In a counting stage as recited in claim 6 wherein said first, second,third, fourth, fifth, sixth, seventh and eighth Nand gates comprisenon-capacitive solid-state elements with the output of the gates beingdirectly connected to the appropriate inputs of the corresponding gates.

9. In a counting stage comprising a plurality of interconnected Nandgates wherein count pulses are supplied to some of said Nand gates tocontrol the outputs of said plurality of interconnected Nand gates andprovide count outputs from at least a single Nand gate as a function ofthe. number of count pulses supplied to said some of said Nand gates,the arrangement for energizing a group within said plurality ofinterconnected Nand gates to shift data therethrough as a function ofthe change of outputs thereof comprising: Nand gating means havingoutputs and inputs; meansfor connecing the ouputs and inputs of saidNand gating means to the respective inputs and outputs of said some ofsaid Nand gates to which said count pulses are supplied and forconnecting the outputs; count inhibit means; means for connecting saidcount inhibit means to some of said first plurality of Nand gates so asto inhibit said Nand gates from pro-' viding outputs of a predeterminedpolarity; shift inhibit means; and means for connecting said shiftinhibit means to said Nand gating means so as to inhibit said Nandgating means from providing outputs of a predetermined polarity wheneversaid stage is operable to count said count pulses supplied thereto.

10-. A system for counting count pulses and for shifting data storedtherein in response to shift pulses supplied thereto comprising: aplurality of stages each stage comprising first, second and thirdpluralities of gating means; means for interconnecting said first,second and third pluralities of gating means of each stage; means forinterconnecting the first and second pluralities of gating means of eachstage With the third and first pluralities of gating means of thepreceding stage thereof; shift inhibiting means for inhibiting thesecond plurality of gating means of each stage from providing outputsignals of a predetermined polarity; count pulse means for providingcount pulses; means for supplying said count pulses to some of thegating means of said first plurality of gating means of the first stageof said plurality of stages for counting said count pulses therein so asto provide count output signals from said system as a function of thenumber of count pulses supplied thereto and the number of stages in saidplurality of stages; count inhibiting means; means for connecting saidcount inhibiting means to the gating means of each of said stages so asto inhibit said gating means from providing output signals of saidpredetermined polarity; and means for supplying shift pulses to saidsome of the gating means of said first polarity of gating means of eachof said stages so as to shift the data stored therein as a function ofthe change in output signals of the gating means in said first andsecond pluralities of gating means of each of said plurality of stages.

11. A system as recited in claim 9 wherein each of said gating meanscomprises a non-capacitive solid-state Nand gate, said system furtherincluding set and reset means connected to at least some of the gatingmeans of at least said first and third pluralities of gating means ofeach stage for setting and resetting the outputs of at least said gatingmeans to predetermined polarities.

References Cited UNITED STATES PATENTS 3,146,345 8/1964 Conover 32837 X3,258,696 6/1966 Heymann 32837 MAYNARD R. WILBUR, Primary Examiner. G.J. MAIER, Assistant Examiner.

1. A COUNTING AND SHIFTING CIRCUIT COMPRISING: A PLURALITY OF GATINGMEANS, EACH GATING MEANS HAVING AN OUTPUT TERMINAL A PLURALITY OF INPUTTERMINALS AND BEING CHARACTERIZED BY PROVIDING AN OUTPUT OF A FIRSTPOLARITY ON SAID OUTPUT TERMINAL WHENEVER NONE OF SAID INPUT TERMINALSIS PROVIDED WITH AN INPUT SIGNAL OF SAID FIRST POLARITY, EACH OF SAIDGATING MEANS BEING CHARACTERIZED BY PROVIDING AN OUTPUT SIGNAL OF ASECOND POLARITY WHENEVER AN INPUT SIGNAL OF SAID FIRST POLARITY ISPROVIDED TO ANY ONE OF THE INPUT TERMINALS THEREOF; MEANS FORINTERCONNECTING SAID FIRST PLURALITY OF GATING MEANS; COUNT INHIBITINGMEANS FOR INHIBITING AT LEAST SOME OF SAID GATING MEANS WHENEVER SAIDPLURALITY OF GATING MEANS IS OPERAABLE IN A SHIFTING MODE; MEANS FORENERGIZING SOME OF SAID GATING MEANS WITH A PLURALITY OF SHIFT PULSES SOAS TO CONTROL THE OUTPUTS OF SAID PLURALITY OF GATING MEANS; SHIFTINHIBITING MEANS FOR INHIBITING AT LEAST SOME OF SAID GATING MEANSWHENEVER SAID CIRCUIT IS OPERABLE IN A COUNTING MODE; AND MEANS FORENERGIZING SOME OF SAID GATING MEANS WITH COUNTING PULSES TO PROVIDEOUTPUT PULSES AS A FUNCTION OF THE NUMBER OF SAID COUNTING PULSESSUPPLIED THERETO.